Recurse Center Week 9

Previous

I'm continuing to work on my circuit design plus circuit construction idea. I have Verilog written to describe a computer architecture I'm now focused on building. Last week, after forcing through tests of an etching method, I built enough confidence to order hopefully the last set of parts and tools. Having this alternating week pattern on and off circuits focus has been great for scaffolding my time.

This week, in the spirit of doing something impossible, I ended up settled on a reverse engineering project limited only to a few days. I've held on to an electric typewriter with the idea of retrofitting it with some data port, so I attempted to interface an FPGA for UART connectivity. The idea being, this typewriter should be capable of printing simple ASCII text/art. I got pretty deep into this, and enjoyed the process, if not completed but now believing to know how it could be done.

2024/10/07

• With circuit construction ideas and constraints fresh in mind, revisited the Verilog circuit implementation.
• This implementation-first perspective allowed for an extremely clear reading. Felt I fully understood Verilog's Register Transfer Logic (RTL) programming model for the first time.
• As co-design of hardware progresses, the Verilog model becomes less abstracted. I'm now curious how to share Verilog modules, and more importantly their testbenches, between this small-scale implementation and an ASIC implementation.
• Continued to read collected papers in Fernandez and Lang's Software-Oriented Computer Architecture. Skipped most papers beyond the abstract, instead reading the introductory essay for each chapter. Learned from historical examples how designs are mostly defined by the limitations they work around.

2024/10/08

• Decided to spend remainder of the delay from shipping, three days, attempting some hardware reverse engineering problem.
• I've been holding on to an electric typewriter and had no idea how it worked. Impulse granted.
• Made good initial progress probing the keyboard's electrical connection. Learned more about using logic analyzers.
• In dis- and re-assembling, a jam happened: the speaker inside generates a continuous error tone. Do some blind connectivity tests, but don't understand what's happened.
• Wanted to spend more of this time working with other people, as I'm now not tethered to the tools at my apartment. I had hoped working on a standalone hardware problem using an FPGA would share the type of development I've been doing. So, with effectively broken hardware, I put debugging this further on pause.

2024/10/09

• Worked in-person, no typewriter in hand, wanting to do anything but my own projects.
• Worked with Konarak on his Verilog implementation of the Nand2Tetris CPU. Enjoyed working with someone doing a related but very different project, giving me a chance to over-share the debugging techniques I've pieced together.
• Talked with Iain over coffee. I was happy to relate some enthusiasm for embedded programming, and hear his perspective on doing both applied and theoretical work.
• Put together and gave a non-programming talk about sheet music.
• Loved Jason's non-programming talk about pop-up books. Didn't get enough time to talk more about origami.

2024/10/10

• Debugged the failing typewriter: header pins had been bent to form a short, acting like a jammed key.
• Readjusted pins and the underlying problem is solved. Everything working as did prior.
• Probed the keyboard wires with a logic analyzer. See some patterns but do not understand them.
• Caught up on writing updates.

2024/10/11

• Rather than interfacing with the combined transmit and receive wires, instead developed enough understanding to emulate transmit signals on the receive wires.
• Quickly uncertain of how to actually trigger and time these transmit signals. Could not find an underlying clock wire to use.
• Retired this reverse engineering work, now at the end of the week. Enjoyed the process and progress.
• Begin more writing. An idea for backfilling content on this website came to me.